1. Technical Field
The present invention relates generally to semiconductor integrated circuit (IC) device fabrication technology and, more particularly, to a semiconductor IC device having a silicide-blocking layer and a related fabrication method.
2. Description of the Related Art
Metal oxide silicon (MOS) transistor, one of the field effect transistors (FETs), is generally composed of a gate placed on a silicon substrate and source/drain regions formed in the substrate at both sides of the gate. According to channel type, MOS transistors are classified into NMOS and PMOS. In addition, there is CMOS (complementary MOS) transistor in which both NMOS and PMOS transistors are formed together in the identical substrate.
In fabrication of such MOS transistors, one of the critical issues is contact resistance between the gate or the source/drain region and metal layers. Silicide, alloys of silicon and metals, has been introduced as contact materials to reduce the contact resistance and thus to improve electrical properties of MOS transistors. Silicide combines the advantageous features of metal contacts (e.g., significantly lower resistivity than polysilicon) and polysilicon contacts (e.g., no electromigration). Silicide may be formed from a variety of metals such as titanium (Ti), cobalt (Co), vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), etc.
As well known in the art, a silicide layer is formed by salicide (i.e., self-aligned silicide) process in which the silicide contacts are formed only in those areas where deposited metal is in direct contact with silicon, and hence self-aligned contacts are obtained.
FIG. 1 shows, in a cross-sectional view, a convention semiconductor device having a suicide layer. Referring to FIG. 1, a field oxide layer 11 is formed in a silicon substrate 10 to define an active region, and a well region 12 is formed in the substrate 10. A gate oxide layer 13 and a gate electrode 14 are then formed on the substrate 10, and low doping parts 15a of source/drain regions 15 are formed in the substrate 10. Dielectric spacers 16 are formed on sidewalls of the gate electrode 14, and high doping parts 15b of the source/drain regions 15 are formed in the substrate 10. Then a suitable metal layer is conformally deposited and subjected to annealing. As a result, a silicide layer 17 is formed on both the gate electrode 14 and the source/drain regions 15.
Such a silicide layer 17 may, however, have the following drawbacks. In a blanket etching process of forming the spacers 16, the field oxide layer 11 may be often damaged at the edges thereof as shown in FIG. 2. Hence the edges of the field oxide layer 11 are relatively lowered than the adjacent source/drain regions 15. That is, the source/drain regions 15 are partly exposed at the edges of the field oxide layer 11. Therefore, the silicide layer 17 may be unfavorably extended to the exposed portion of the source/drain regions 15. This extended portion of the silicide layer 17 may provide a path of leakage current, consequently degrading the characteristic of the device.